Try the following:
1. Set up your logic analyzer with a short sampling duration of no more than 1 a few milliseconds
2. Use a sampling rate of 5 Mhz or higher to get sufficient resolution, no external clock. Set the threshold to 2.5V
3. Capture A0 - A9, and RST. If possible also look at PSEN to help to pick when valid address is present. But it will be pretty obvious even without PSEN
4. Triger on the falling edge of the RST signal
5. Power up the DME. That should start the capture.
In my logic analyzer I see RTS coming up to logic 1 (5V) and then go to logic 0 (0V). That is when the uC starts up. Shortly thereafter you see PSEN with a 1 Mhz pulse train. The address signals are valid on the falling edge of PSEN. You can see that the first byte is read in one machine cycle and the LJMP instruction takes 2 machine cycles to execute. That is why you see address 0x0002 being there twice.
One more thing. The original 8051 uses 12 clock cycles for one machine cycle. Each instruction takes one or multiple machine cycles to execute. If you are using a modern 8051 it might run more efficiently through the code and might make the logic trace look a bit different.